Results and files
Files and the code panel
Where the module, testbench, simulation log and synthesis report end up.
Everything a run produces ends up in the panel on the right of the chat, sorted into tabs. It stays with the chat, so you can come back to a generation from last week and the files are still there.
The tabs
counter_8bit.sv
module counter_8bit (
input logic clk,
input logic rst_n,
input logic en,
output logic [7:0] count
);| Tab | What is in it |
|---|---|
| Module | The generated RTL. The file you came for. |
| Testbench | The self-checking testbench, when Auto-Verify was on. |
| Simulation | The simulator's log, including every assertion that passed or failed. |
| Synthesis | The synthesis output and the resource estimate for your target. |
When a tab holds more than one file, a row of filenames appears under the tab strip. That happens on designs split across a package and a module, or when a run wrote more than one testbench.
A sensible reading order
- 1
Module, port list first
Widths, directions and parameter defaults. A misread specification shows up here before anywhere else.
- 2
Simulation, bottom first
The summary line at the end tells you how many checks ran and how many failed. Scroll up only if something failed.
- 3
Testbench, if the result surprised you
A pass with three assertions and a pass with twenty are different things. The testbench is where you find out which one you got.
- 4
Synthesis, for shape
Look for numbers far from what you expected rather than at the numbers themselves; see Language and target device.
Downloading
Download all at the bottom of the panel builds one zip on the server and hands it to you as a single file. It is not a stack of separate browser downloads, and the archive is flat; files with the same display name are suffixed rather than overwritten.
You can also copy any single file straight from the viewer with the copy button.
Giving the conversation more room
The panel collapses to a narrow rail with the icon in its top corner, which is worth doing while you are writing a long follow-up. Expanding it again puts you back on the tab you were reading.
When the panel is empty
| What you see | Why |
|---|---|
| Generated files will show up here once a run completes | The chat has not produced files yet; either the run is still going or the last turn was a question. |
| Only a Module tab | Auto-Verify was off, so no testbench, simulation or synthesis output exists. |
| A change report instead of tabs | This is a project chat. See Reading the change report. |