Configuring a run

Language and target device

Verilog or VHDL, and the vendor family your synthesis estimate is measured against.

Two settings that shape the output rather than the process: which language the module is written in, and which device family the synthesis estimate is measured against.

Output language

Choice	What you get
Verilog	Verilog and SystemVerilog, written to synthesise. Files use the .sv extension. Available in every mode.
VHDL	VHDL, files use the .vhd extension. Available in Plan mode only, from a scratch workspace.

Heads up

VHDL runs cannot use the IP Core Library or the Knowledge Base; both switches are unavailable while VHDL is selected. Everything else, including Auto-Verify and Reflection, works the same way.

Set your usual language in Settings under Setup so you are not choosing it every run, and override it in Run setup when you need the other one.

Target device

The target is picked at vendor granularity, not per part. That is deliberate: the estimate comes from a synthesis script chosen by vendor, and naming a specific part would imply a precision the flow does not have. Family members share resource characteristics closely enough for a rough estimate to stay honest.

Target	Estimated against
AMD / Xilinx	7-series LUTs
Intel / Altera	MAX 10 LUTs
Lattice	ECP5 LUTs
Gowin	Gowin LUTs
Generic ASIC	Generic gates

Reading the synthesis report

The report is a sanity check, not a place-and-route result. Read it for shape rather than for numbers you would put in a spreadsheet:

A LUT count far above what you expected usually means an unintended latch, an oversized counter, or a multiplier where you assumed a shift.
Inferred block RAM or DSP blocks appearing where you did not want them is worth a follow-up.
Zero registers on a design you described as registered means the reset or clocking was misread.

An excerpt from a synthesis report

=== counter_8bit ===
   Number of wires:                 14
   Number of cells:                 27
     $_DFF_P_                        8
     $_ANDNOT_                       9
   Estimated LUT usage:              9

What the target does not do

Picking a vendor does not add vendor primitives to your module, and it does not tie the RTL to that family. The generated code stays portable; the target only decides which synthesis script produces the estimate.