Getting started
Quickstart
Go from an empty box to a simulated, synthesis-checked module in about five minutes.
This walks through one complete generation: an 8-bit counter, written, tested, simulated and checked against a synthesis target. It costs one run from your free credit, and it takes about five minutes including the reading.
Before you start
- A verified account. If you do not have one, create one first.
- Some credit or an active plan. New accounts start with $1.00, which covers this.
Generate your first module
- 1
Open a new chat
Press New chat at the top of the sidebar. You land on a screen asking what you are building.
- 2
Leave the workspace on From scratch
The switch above the composer picks between writing a new module and editing an existing project. For a first run, stay on the left.
From scratchExisting project - 3
Describe the module
Type something specific enough to be checkable. For this walkthrough, use this:
8-bit up counter with a synchronous active-low reset and an enable. Count wraps to zero after 255.
- 4
Turn on Auto-Verify
Open Tools under the composer and switch on Auto-Verify. Without it you get a module; with it you get a module the simulator agreed with.
- 5
Press Generate
The run opens its own chat and starts working. You will see the seven steps move from SPEC through to FILES.
8-bit up counter with synchronous reset and an enable
AgentPlanClaude Sonnet 5Tools · 1Generate - 6
Read the result
When the run finishes, the panel on the right holds the files. Start with the Module tab, then Simulation to see what the testbench actually proved.
- 7
Ask for a change
Type a follow-up in the same chat, for example add a terminal-count output that pulses high on 255. The next run starts from the module you already have.
What to look at in the output
Before you paste anything into a real project, skim these four things:
- The port list. Widths and directions are where a misread spec shows up first.
- The reset. Synchronous or asynchronous, active high or low; make sure it matches the rest of your design.
- The simulation verdict. A pass with two assertions is not the same as a pass with twenty.
- The synthesis report. A resource estimate wildly larger than you expected usually means an unintended latch or a wide multiplier.