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Troubleshooting

The failures people actually hit, and what to do about each one.

The problems people actually run into, and what to do about each. If yours is not here, get in touch; a case that is missing from this page is a gap worth closing.

A run failed

What you see	What to do
The run stopped on RTL	The module could not be written to a state that compiles. Usually a spec asking for something contradictory; re-read it, then say the requirement more directly.
The run stopped on SIM	The design and testbench did not compile together. Ask for the fix as a follow-up; the failing log goes with it and it is usually resolved in one turn.
The run stopped on SYNTH	Something in the design will not synthesise, often a construct that is simulation-only. Ask for a synthesisable version.
The run finished but the module is wrong	Not a failure; a specification problem. Say what is wrong in a follow-up rather than starting over. See Writing a good spec.
The run seems stuck	Long runs are normal with Auto-Verify and Reflection on, especially in project mode. Give it a few minutes before assuming it is wedged; the step indicator tells you where it is.

A run would not start

Message	Meaning
Not enough credit to start a run	Your balance is below the minimum needed for a run to finish. Add credit or pick a package; see Credit and referrals.
Your monthly allowance is used up	The allowance is gone and there is no credit to cover overage. Top up, or wait for the period to renew.
Payment failed; update your card	The subscription is past due. Update the card in the Stripe portal from the billing page.
Upload a project first, or switch to From scratch	The workspace toggle is on Existing project but no archive has been uploaded yet.

A project upload was rejected

Problem	Fix
Please choose a .zip	Only zip archives are accepted; tar and 7z are not.
Too many files	A build or dependency directory almost certainly came along. Check the skipped list and re-zip without it.
Archive too large	Remove generated output, simulation dumps and waveform files; they are the usual weight.
A file I need is in the skipped list	It was filtered or rejected. See Limits and retention for what is filtered and why.
My paths look wrong	A wrapper directory was probably unwrapped, or not unwrapped when you expected it. The upload card tells you which happened.

Account and access

Problem	Fix
The verification code never arrived	Check spam, then use Resend code. If the address was wrong, use Wrong address? on the same screen.
Please verify your email first	The account exists but was never confirmed. Finish verification.
I get logged out repeatedly	Third-party cookie blocking or an aggressive privacy extension is the usual cause. Allow cookies for this site.
Google or GitHub sign-in does nothing	Those providers are not connected yet. Use email and password for now.

The interface is doing something odd

A chat will not delete. It has a run in progress. Wait for the run to finish or fail.
The code panel is empty after a run. The last turn was a question rather than a generation, or Auto-Verify was off and there is only a module.
VHDL is not selectable. You are in Agent mode or project mode. Switch to Plan mode in a scratch chat.
Two tool switches are greyed out. The output language is VHDL; the IP Core Library and the Knowledge Base do not cover it.
My saved defaults do not seem to apply. They apply to new chats; an existing chat keeps whatever the composer currently shows.

Results are consistently disappointing

Before changing models, check these in order:

Is Auto-Verify on? Without it nothing checks the module and problems reach you instead.
Does the spec pin down reset, widths and latency? Those three account for most rework.
Are you iterating in one chat, or restarting? Follow-ups keep everything that was already right.
Is your coding style set? Repeating conventions in prose is less reliable than saving them once.
Only then: try a larger generator model, or switch on Reflection.